1. Field of the Invention
The present invention relates to non-volatile memory devices, such as flash memory based on floating gate memory transistors; and more particularly to processes for reading data from a non-volatile memory device while writing data to the same device.
2. Description of Related Art
One class of non-volatile memory device is referred to as flash memory. Flash memory is electrically erasable and programmable. The erase process in flash memory is applied to large blocks of cells at the same time, and has been called flash erase. Flash memory devices are typically manufactured using floating gate transistors, in which the erase process requires a significant amount of time to execute. By erasing a large block of memory cells at the same time, significant speed improvement is provided over other types of non-volatile memory devices using floating gate transistors. Also, the process of programming data in flash memory devices is a relatively time-consuming process.
One disadvantage of traditional flash memory arises from the relatively time-consuming processes of erasing and programming the devices. While these processes are being executed at one addressed location on the device, the rest of the memory cannot be used. The host processor is often idle while the flash memory is being programmed or erased.
Technology has developed to allow reading data from one set of memory cells on an integrated circuit while erasing or programming another set of memory cells. This prior art is represented by U.S. Pat. No. 5,245,572, entitled FLOATING GATE NON-VOLATILE MEMORY WITH READING WHILE WRITING CAPABILITY. Read while write capability allows the host processor to use the memory device for specific kinds of access, even while programming or erasing operations are occurring.
The prior art approaches require two separate memory arrays, having independent address decoders. In addition, the prior art approaches require separate address registers connected to the address inputs on the device, for the respective address decoders. Having the parallel address registers, address decoders, memory array structures allows the control logic on the chip to execute one process on one of the parallel arrays, while allowing the reading data from another of the parallel arrays. However, this duplicity comes at the cost of additional area and complexity on the integrated circuit, and consequently additional cost in manufacturing.
Therefore, it is desirable to provide non-volatile memory integrated circuit which is capable of reading while writing, which has a more efficient implementation, and which consumes less area on the integrated circuit.